The short-channel CMOS processes usually used during the production of analog-to-digital converters are optimized to high transistor component densities and high switching speeds. In particular in the area of ASIC design, however, the further processing of an item of analog input information increasingly requires high-resolution and also precise analog-to-digital converters. As a result of how the process is carried out, high-precision analog components, such as for example resistors and capacitors, are available only in very rare cases. Therefore, in order to achieve accuracies beyond the limit of 8 bits, an adjustment method has to be provided, the type of adjustment essentially determining the quality and reliability of the converter. Binary weighted capacitor arrays are often used in analog-to-digital converters. However, inaccuracies in the weighting ratio of the capacitances inevitably lead to faulty conversion results. These errors result in differential nonlinearities (DNL) which often exceed the specified framework. A 12-bit converter can for example be specified with a precision of 1/2 or 1/4 LSB, it being possible that discrepancies in the capacitive array which controls the upper 8 bits lead to faults of a couple of 10 LSB.
The following printed publications:
(1) LEE H.S., Hodges D.A., "Self-Calibration Technique for A/D converter", IEEE CAS-30, pp. 188-190, March 1983 PA0 (2) Tsukada T., Takagi K., Kita Y., Nagata M., "An Automatic Error Cancellation Technique for Higher Accuracy A/D Converters", IEEE, Journal of Solid-State-Circuits, Vol. SC-19, No. 2, pp. 266-268, April 1984 PA0 (3) Matsuya Y., Akazawa Y., Iwata A., "High-Linearity and High-Speed CMOS 1-chip A/D, D/A Converter. All-Digital Linearity Error Correction (LECS)", Electronics and Communications in Japan, Part 2, Vol. 70, pp. 73-84, 1987 PA0 (4) McCreary J. L., Gray P. R., "A High-Speed, All-MOS Successive Approximation Weighted Capacitor A/D Conversion Technique" ISSCC Dig. Tech. Papers, pp. 38-39, February 1975 PA0 (5) McCreary J. L., Gray P. R., "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part I", IEEE SC-10 pp. 371-379, December 1979
disclose correction methods for capacitance arrays in analog-to-digital converters, all of which use an additional digital-to-analog converter. In the case of known correction methods, the capacitor array is corrected in its entirety, but not the individual capacitances independently of the capacitance deviations of the others. Consequently, a recalibration is not possible during normal operation without a relatively long interruption of the conversion process.
European Patent Application No. 0 064 147 A3 describes an analog-to-digital converter in which a multiplicity of similar capacitors are used, where the capacitance values are in each case halved from component to component. The component with the smallest place value is present twice. By applying potentials, a predetermined component is compared with the remaining components of lower place value in that the potential which then appears at the capacitors is compared with a reference potential. In this process, all capacitors are compared with each other successively.